1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and to a method for manufacturing the nonvolatile semiconductor memory device.
2. Description of Related Art
A highly-integrated nonvolatile semiconductor memory device has been demanded with higher function and performance of an information processing device. A technique of miniaturizing memory elements that configure the nonvolatile semiconductor memory device has been known as an example of a technique for enhancing the integration degree of the nonvolatile semiconductor memory device (for example, refer to JP-A-2003-234422).
JP-A-2003-234422 discloses a technique by which a nonvolatile memory device is formed through a self-aligning method. JP-A-2003-234422 discloses a technique pertaining to a nonvolatile floating gate memory cell array which is remarkably reduced in cell size without adversely compromising the erase/couple ratio of the memory cells. In JP-A-2003-234422, each of the memory cells disposed in the semiconductor device includes a trench formed on the surface of a semiconductor substrate, and source and drain regions apart from each other. A channel region is formed between the source and drain regions. The drain region is formed below the trench. The conductive floating gate is formed on a part of the channel region, isolation is made therefrom, and an edge directed horizontally extends therefrom. A conductive control gate is formed, and includes a first portion arranged in the trench, and a second portion arranged adjacent to the edge of the floating gate and isolated therefrom.